Diodes of planar structure type are known which have a higher diffusion concentration of impurity in the central area than that in the periphery area in which a PN junction is formed to generate a breakdown in the central area. Such diodes of PN junction have been expected to indicate the improved reliability in quality compared with diodes of mesa structure which have a slope formed on side surfaces of the semiconductor substrate to expose outward the PN junction on the slope.
FIG. 11 shows a structure of a diode device shown by International Patent Publication WO 03/081681. Shown diode device 10 comprises a first semiconducting region 1 of N+conductivity type; a second semiconducting region 2 of P+conductivity type formed over one main surface of first semiconducting region 1; and a third semiconducting region 3 of N−conductivity type formed between first and second semiconducting regions 1 and 2 and having the thinner diffusion concentration than those of first and second semiconducting regions 1 and 2. Second semiconducting region 2 comprises a bowl portion 2a which has a flat bottom surface 2d directly joined on first semiconducting region 1 and partially spherical surface 2b, and a flat flange portion 2c enveloping bowl portion 2a and positioned over first semiconducting region 1 through third semiconducting region 3. A first electrode 5 is formed on a whole main (upper) surface of second semiconducting region 2, and a second electrode 6 is formed on the other (bottom) surface of first semiconducting region 1. A recess 7 is formed at the center of an upper surface of diode device 10, and an inner junction region 8 is formed in direct PN junctions between a bowl surface 1a of first semiconducting region 1 and flat bottom surface 2d of second semiconducting region 2 and between bowl surface 1a of first semiconducting region 1 and spherical surface 2b of second semiconducting region 2. In other words, inner junction region 8 forms a flat or bowl-shaped direct PN junction interface between first and second semiconducting regions 1 and 2 which both have the higher diffusion concentration of impurity than that of third semiconducting region 3 to provide a desirable endurance against high voltage or breakdown as estimated based on first and second semiconducting regions 1 and 2. Not shown, but third semiconducting region 3 is formed into an annular shape in an imaginary plan view, enveloping inner junction region 8 and being in direct contact to second semiconducting region 2 to form an outer junction region 9 in cooperation with second semiconducting region 2. Third semiconducting region 3 comprises a tapered surface 3a convergent toward bowl surface 1a of first semiconducting region 1, and a flat surface 3b enveloping tapered surface 3a to form PN junctions between second semiconducting region 2 and tapered surface 3a and between second semiconducting region 2 and flat surface 3b. Outer junction region 9 has outer surfaces 9a exposed outward on side surfaces of a semiconductor substrate 4. In operation of diode device 10, outer junction region 9 serves to allow a depletion layer (not shown) to widely spread from outer junction region 9 between second and third semiconducting regions 2 and 3, in particular, extensively expanding into third semiconducting region 3 of thin diffusion concentration of impurity.
In another aspect, Japanese Patent Disclosure No. 2002-185016 represents a diode device provided with a silicon substrate 11 which, as shown in FIG. 12, comprises a first semiconducting region 12 of N+conductivity type formed at the bottom of silicon substrate 11; a second semiconducting region 13 of P+conductivity type formed over first semiconducting region 12; a third semiconducting region 15 of N−conductivity type formed between first and second semiconducting region 12 and 13; and a fourth semiconducting region 14 of N+conductivity type formed inside of third semiconducting region 15 and between first and second semiconducting regions 12 and 13. Fourth semiconducting region 14 has the higher diffusion concentration than that of surrounding third semiconducting region 15. A first electrode 16 is formed on an upper surface of second semiconducting region 13, and a second electrode 17 is formed on a bottom surface of first semiconducting region 12.
Diode device 10 shown in FIG. 11 is defective because recess 7 provides diode device 10 with a complicated sectional structure, and makes it difficult to form first electrode 5 into a desirable shape when recess 7 is formed at the center on upper surface of semiconductor substrate 4. Also, another problem arises that mechanical stresses disadvantageously concentrate on recess 7, and may invite crystal defects in semiconductor substrate 4, thereby resulting in deterioration in electric property. In addition, as diode device 10 requires a specific processing for silicon etching in manufacture to form recess 7 on upper surface of semiconductor substrate 4, such processing is troublesome, and cannot provide a more stable shape of semiconductor substrate 4 than that of a typical planar structure.
In diode device shown in FIG. 12, as the same diffusion concentration of impurity is given along PN junction interface 18 from outermost points of breakdown area 20 at the center of PN junction interface 18 to outer peripheral surfaces 19 of silicon substrate 11, breakdown may be propagated to outer peripheral surfaces 19. In mechanically dicing silicon substrate 11 by means of diamond blades to cut and separate it into many semiconductor chips, dicing operation tends to produce cracks or breaks on outer peripheral surfaces 19. Also, foreign matters such as dust, dirt or cut scraps including ions tend to attach to outer peripheral surfaces 19 without protective film thereon. Accordingly, propagation of breakdown to outer peripheral surfaces 19, moves or changes the breakdown voltage, and therefore, diode device 10 cannot indicate a high and stable voltage endurance. In addition, there is a risk that excessive reverse current flows along outer peripheral surfaces 19 of silicon substrate 11 to damage or burn silicon substrate 11 with reverse current.
An object of the present invention is to provide a semiconductor device capable of controlling leakage current and having a stable voltage endurance, and a method of easy manufacture therefor.